STE video chip

[exxos]

Another thought which may work the same as replacing the chips with LS types, is adding something like 10-33R in series with the power pins. If the current is reduced, then it may be enough reduction on ground spiking to get things working again. Will try and find some time to test that out as well.

Still no progress from JLC

[exxos]

Tried 40R (YMMV) in series with the F374 power (Using the 1712 shifter)

IMG_0318.JPG (316.96 KiB) Viewed 3350 times

BEFORE (STOCK)

IMG_0309.JPG (276.85 KiB) Viewed 3350 times

AFTER (40R)

IMG_0317.JPG (333.61 KiB) Viewed 3350 times

40R WITH GND WIRE

IMG_0319.JPG (250.32 KiB) Viewed 3350 times

The 40R also solves the crackling sound with the 1712. When the F374 latches (on the rise) there is a noticeable reduction in noise when using the 40R in the F374 power rails. Adding the GND wire does improve things as well.

Proof is in the pudding as they say:

[Steve]

Congrats @exxos this is brilliant, i'll be implementing both the GND and +5v resistor fix to my STe's straight away. I see with the resistor fix you just lift the +V leg out of the socket and solder the leg to the resistor and then to the +5v side of the ceramic caps behind right? Just checking.

[exxos]

Congrats @exxos this is brilliant, ill be implementing both the GND and +5v resistor fix to my STe's straight away. I see with the resistor fix you just lift the +V leg out of the socket and solder the leg to the resistor and then to the +5v side of the ceramic caps behind right? Just checking.

Thanks. Yeah just lift the 5V leg (I guess you would have to carefully cut it and lift the leg if its soldered in) and run 5V via 40R. 40R was just what I had to hand (roll of the dice value) but likely 47R or a little higher (maybe 68R) will likely be fine as well (but I only tested 40R) .

[exxos]

Out of curiosity I had a quick look for the differences on the output stage of the LS vs F series chips.

A quick Google-foo resulted in this.

LS.JPG (22.48 KiB) Viewed 3310 times

F.JPG (31.32 KiB) Viewed 3310 times

It is the resistor at the top right I was interested in. It has been a couple of decades since I looked at all this stuff.. I thought the F-series did not have any resistor in series with the output stage but according to that schematic it does (***). 45R on the F-series and 120R on the LS series. So I guess 120-45=75R would be the active difference there.

*** I am probably thinking of the problem of MOSFET drivers which without deadtime can short out the power rails causing huge spikes. You would have to imagine that resistor is not there at all and then you have two transistors in series with the power rail with the transition of one turning off and the other turning on creates moment three short across the supply rail causes the voltage spikes etc

[exxos]

Buffer boards finally shipped! Should be here thursday!

[Badwolf]

Incidentally, I've been seeing this a bit fiddling with my RAM/booster board.

Is this possibly related to that clock skew problem or is this more like my board messing something up, you think?

(I've the -712)

IMG_5113.jpeg (68.38 KiB) Viewed 3260 times

BW

[exxos]

Incidentally, I've been seeing this a bit fiddling with my RAM/booster board.

Is this possibly related to that clock skew problem or is this more like my board messing something up, you think?

I have seen that right from the start with the boosters, but also on stock machines. It mostly seems random when the machine is powered on. But its been so rare that I've not been able to look into it. But most likely is down to the clock skew.

[exxos]

Looky what just arrived..

IMG_0360.JPG (129.14 KiB) Viewed 3180 times

[exxos]

A quick "bodge it in test".

IMG_0369.JPG (263.45 KiB) Viewed 3166 times

BEFORE MOD

IMG_0361.JPG (287.52 KiB) Viewed 3166 times

AFTER MOD

IMG_0368.JPG (336.44 KiB) Viewed 3166 times

So indeed this does solve the problem with the 1712 shifter. I also tried the 588 and it still works fine.

I tried various combinations of delays. Long story short, buffering and double buffering does not do anything at all. The buffer delay seems to be incredibly small to make pretty much insignificant. It needs the extra delay there. The problem is the clock edges are still not synchronised because I should have used a inverter instead of a buffer So I cannot actually do the experiment I wanted to. But changing the delay does make and break the graphics corruption, so these boards are still usable.