TF536 and H4 Benchmark

Benchmark screenshots for various boosters & machines.
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exxos
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Re: TF536 and H4 Benchmark

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TF536 ST edition - MAPROM1.8E - TOS206

IMG_0358.JPG
IMG_0358.JPG (381.91 KiB) Viewed 2667 times
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Re: TF536 and H4 Benchmark

Post by Cyprian »

Interesting figures.

I wonder why the best results are with Instruction Cache Off. - D ON, I OFF
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Re: TF536 and H4 Benchmark

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Cyprian wrote: Mon Feb 14, 2022 8:15 am Interesting figures.

I wonder why the best results are with Instruction Cache Off. - D ON, I OFF
No idea. But IIRC on the falcon the data cache on made the tests about 3% slower. So caches don't always help.
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Re: TF536 and H4 Benchmark

Post by alexh »

Cyprian wrote: Mon Feb 14, 2022 8:15 am I wonder why the best results are with Instruction Cache Off. - D ON, I OFF
Cache line fills from DRAM take more time than a single instruction fetch. Even with 030 burst mode. That time is usually made up when the CPU executes the full line from CACHE and doesn't read from DRAM. If the CPU doesn't execute a full cache line, perhaps due to branching, then the benefit of the cache is reduced. Even more so if that cache line becomes invalidated and re-filled due to code alignment. (Sometimes called cache thrashing) So depending on the code, iCache performance can be worse than no iCache.
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Re: TF536 and H4 Benchmark

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