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In light of the problems with the GAL's with the STE booster V1 series, Which have uncovered another DMA problem , I started a couple weeks ago changing out the GAL for a "more modern" ATF1502 PLD. I think the tolerances and specifications should be a lot more stable with those than the older GALs. It will also allow me to do more logic fiddling inside and I'm capable of doing with the 22V10 GAL.
Though the problem was, I thought I might as well add ROM on board as I had more IOs. Which turned out to be not so simple, because I did not have enough IOs to decode the entire address bus to get address zero for the ROM for booting. I did not want to have the hassle of soldering a wire to the ROM_CE signal on the ROM sockets ( basically like I do with the V1) So I got a little creative and ran the lower address lines through a chain of OR-GATEs so I could at least detect that they were all zero and check the high address lines through the PLD. While I was doing that I thought I might as well add SRAM on there as well
So now it has turned into another totally new project which I don't have time for 
It would be extremely useful if some kind soul out there to lend a hand multiple respects. Mostly someone who as a quality logic analyser who can measure some signals on the STE (with internal blitter for starters) who also has a booster who can take the same measurements again and see if there is any discrepancies between both the datasets.
This is going to be the stalling point for any new existing boosters including the TF536 STE port. Basically because the 8MHz clock will always be running through some logic and in slowing this down seems to cause DMA issues. This is what I was talking about in my blog that it does not make sense but unfortunately this issue needs investigating before anything else. This could be ongoing for months or even years or may never get resolved at all. So currently I do want to produce any new boosters for the STE until this problem is understood and properly resolved.
Incidentally, in case people have not read my blog or the Pico hard drive threads, the allegedly "GOOD DMA" does not work either and actually makes the problem worse. So this isn't the usual "BAD DMA" type of DMA issue. It is something completely different it seems.
I have already done a massive amount of testing In the other threads,and how it seems is that the bus grant logic has to happen at precisely the same time as it does as the stock 8MHz system does. Theoretically it should not make any difference but there is currently no other theories or explanations as to why this happens.
I can only assume that when the CPU is slightly de-synchronised from the GST MCU, something internally trips up. Maybe BG from the CPU falls to close to a clock edge and screws up where is normally it wouldn't . This is why a logic analyser trace of the signals is needed with and without the booster to make a start on properly diagnosing the problem.