I'm about ready to push the button on PCB production for DFB1r5, but since revision 4 made the project functionally complete (albeit with some bodge wires and trace cutting needed), I think it's time to open up the hardware source to the collective wisdom of the board so, with luck, there doesn't need to be a revision 6.
To that end, below is a PDF render of the schematic and the Kicad files have been published on my GitHub: https://github.com/dh219/DFB
Should anyone with hardware design experience wish to take a look and spots any obvious brainfarts on my part, please do speak up. I'm hoping to press go on the order towards the end of this week coming (week ending 21st January 2022).
For example on my last revision, I put a top byte line on the second from top byte of my RAM buffers, and vice versa. I also wired up A0 on the FPU instead of tying it to VCC.
These are the sorts of things I'm hoping to avoid by opening the source early.
Changes to this from the last revision (see https://www.exxosforum.co.uk/forum/viewt ... =29&t=4532) include:-
- FCx correctly joined;
- Optional pullups on the bus arb lines & reset;
- Optional SMD resistors on clocks;
- Declutter FB5 on CPLD;
- Second optional OSC for FPU;
- Cuttable BGI/BGO bridge;
- Corrected FPU lines;
- Corrected RAM data lines;
- Reordered ROM lines;
- Reduced number of fixed pull-ups: direct to VCC where possible.
- Be a plug-in board requiring no soldering on the Falcon;
- Increase available RAM beyond the 14MB the stock Falcon can be expanded to;
- Be low cost;
- Provide some acceleration;
- Allow the PSU to remain in the case;
- Be open source.
Thanks,
BW.