- The LaST Upgrade -

PART 25 - Falcon Clock Patch

Last updated February 29, 2024

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The V4 clock buffer was born from extensive research which is documented towards the bottom of this page. V4 aims to work on more problematic falcons where the more standard patches may fail. The FPU and SDMA clock are cleaned up and amplified which a higher output drive capability. Signals are correctly balanced to give very clean waveforms as illustrated below.

The Falcon V4.x clock patch installs basically the same as outlined in the V2 install below. However, there are some aditions. These address new problems which have been recently diagnosed. The V4 patch is more complicated to install than other solutions simply because it addresses and fixes more problems than the original clock patch designs.



Look for the pads as highlighted in the image above under the FPU (on the bottom of the motherboard) and solder in the 100pF capacitor as illustrated.



Basically you need to cut the "bootleg" track as shown. Solder in a 0805 68R resistor over the now cut tracks. Then solder the 47pF capacitor as show in the images below.


Make sure the capacitor legs do not short out on anything on the PCB!


NOTE: 62R resistory may be supplied with a 68R resistor or similar value.

V4 can be purchased HERE.





Installing is pretty simple. At least on machines which haven't already got a patch installed. The problem I found was super glue was used to glue the wires down, so removing the old patch caused damaged to the PCB tracks and pads. I was lucky and the PCB VIA's were still in place to solder to.

If you are doing this update to a virgin Falcon, then you will need to remove 3 SMT resistors. R221,R222,R216. I would suggest just blobbing a huge blob of solder of the SMT resistor then you can GENTLY push it off the pads once all the solder has melted. Once all 3 SMT resistors are off, GENTLY clean the area with a IPA swab and check for pad damage under a magnifier. If you have damaged pads then I would suggest you abort the install as "trying to fit it" will likely destroy your falcon incurring a hefty repair bill!

DISCLAIMER. Installing this patch along with removing the old patch is done entirely at your own risk. I do not accept any responsibility if you kill your falcon while doing these modifications.


The buffer board comes assembled so you don't need to worry about soldering the SMT parts.

I suggest you remove the U63 to make it easier to solder the patch board onto the IC. 0V marked on the PCB is pin 10 as shown in the above image. Then the diagonal pin 20 is the 5V pin marked on the PCB. Make double sure pin 1 of the IC is to the left as orientated in the above image. Getting this step wrong and soldering the buffer board on backwards is not a good idea, so check and check again! The PCB needs to sit flat ontop of the U68 IC. So solder as illustrated in the above image.

TIP: I would suggest placing the 2 header pins in the buffer PCB and soldering them on the bottom of the PCB to hold them in place while soldering to the IC. I would also suggest as you likely need 3 hands to solder this, that you put a little solder on the IC pin and header pin, then you can hold the IC and PCB together in one hand and just heat up the 2 solder joins and melt them into 1. Then once held in place, solder the other pin and add a little more solder if needed.

TIP2: Make sure the header pin is just long enough to overlap the wider top part of the IC legs.

WARNING: DO NOT get solder on the narrower part of the IC pins which push into the socket. Only solder to the wider top half of the IC pins. If you get solder on the part of the pin which pushes into the IC socket, then clean it off, otherwise you will likely damage the IC socket and the IC wont contact properly! (this would be very bad!) .

WARNING: Double make sure you have not shorted out the IC pins next to where you are soldering the PCB header pins.

NOTE: Its unlikely to be able to solder the PCB ontop of the IC perfectly straight.



Trim the header pins and solder them on the top side of the PCB. Do not get the pins too hot otherwise it may melt the solder on the bottom side of the header pins and you likely will have to re-solder the bottom half of the pins again. Trim the tops of the pins once done.

Place the U63 & buffer PCB back into the socket. The first wire is marked with 2 red circles. I supply a small length of wire so cut to size (as short as possible) and solder the wire as shown above.


2nd wire to solder on.

NOTE: I circled the PAD as this is where the wire is supposed to go, but due to pad damage I had to solder to the VIA, hence the red arrow showing where I actually soldered it to.


3rd wire.

NOTE: I circled the PAD as this is where the wire is supposed to go, but due to pad damage I had to solder to the VIA instead.


4th wire.

NOTE: I circled the PAD as this is where the wire is supposed to go, but due to pad damage I had to solder to the VIA instead.

Also a modification to the falcon needs to be done and shown HERE

Later builds of the board have a jumper which is shown HERE.

Double check all your connections under a magnifier. Turn on your falcon and it should power up as normal. I've noticed the Falcon seems to take 2-5 seconds to output a display on my monitor, so it can make you worried when it doesn't output a white screen as soon as your power on! Though if your falcon has not come on within 5 seconds then turn off your falcon as you likely have done something wrong or damaged something. In which case, good luck ;)






https://youtu.be/wSL-1w9aW4k by mzry (Steven Timms )

http://www.stcarchiv.de/stc1998/06/falcon-beschleunigen Interesting read about clock patches. (thanks Mikro)




I have had a report of DSP sound issues on one particular Falcon. The symptom was crackling audio before and after fitting the clock patch. There was also some intermittent lock-ups and crashes after fitting. This was a voltage drift issue which only seems to happen on some machines. This mod needs to be done to all V2 and V3 series exxos boards to avoid any potential issues ;)

The solution is in the image which shows a simple 0805 or 1/8 watt leaded 100K resistor which is soldered on the "bootleg" track. The white wire connects to 0V as shown.

Early V2 production runs were not supplied with the resistor. Later V2 production runs were supplied with both 0805 and leaded resistor to let the user choose which they prefer. V3 series is supplied with leaded resistor only.




V3 is almost functionally identical as the previous V2. Only it has a extra pad for the SDMA clock line delay. Configuration is as below.

DELAY OFF = 7ns default delay of the IC. Recommended configuration for stock machines.
DELAY ON = 14ns (2 Gate delay). - For experimenters only.
EX-DELAY = 24ns total delay (14ns + 10ns extra) For experimenters only. V3 CLOCK PATCH ONLY

V3 still requires the 100K pulldown resistor on the SDMA clock line as illustrated HERE.



OLDER V2 HISTORY - October 31, 2016

I found there was some bad ringing on the Falcon clocks. So I designed a small PCB which has some buffer resistors and also makes the upgrade a bit neater.

If there is enough interest I will make up a small batch of these PCBs.

I also found a interesting page here which has 3 different ways this clock patch has been done. http://members.optusnet.com.au/~startreks/falccct.html

Also official Atari info here METHOD1 & METHOD2

I did not see "method 3" when I created by design. Though it seems steinberg recommended using buffer resistors. I added those onto my PCB anyway as I saw there is bad ringing on the clock signals. So this mod is a lot better than previous methods.


November 17, 2016

Above is the test board in place. This version has a typo as R216B should have been R216T. Where T=TOP of the resistor and B=Bottom of the resistor on the falcons motherboard. As my falcon already had the patch done shown at the start of this page, I had to removed it. unfortunately it was death by superglue and the PCB pads came off :-( However its not a pad thing really as there as via's right next to the pads, which I think make a more secure connection to solder to anyway.

The middle scope image shows the Falcons default clock waveform, which also is the same as the output of the F04 without resistors. The second scope image on the right shows with the resistors added. As you can see the bottom of the waveform has almost 1volt of "bounce" and this is likely being seen by parts of the falcon's motherboard as a HI when it is in fact a LOW. Similar issues were riddled with the ST line aswell. Its clear Atari has some thoughts to add resistors on the motherboard to start with, but didn't quite get there into having stable clocks.

I have noticed that the 3 clock outputs need different values of resistors, so I need to experiment a little to find the best values, but its very close with the values I guessed at anyway :)

March 21, 2019

The "Blue Edition" Version 2 fits the same as the previous V1 (purple) board.

Version 2 solves a poor logic low level on the SDMA clock line.

The solder pad turns on/off a 3 gate delay which should simulate the delays of the second chip on the phantom making this board a "all in one" solution. This has now been confirmed to work with the Phantom (thanks Steve!)

How does it work ?

Problem is as always noise and grounding problems. You actually end up with something like 2v DC offset between the clock source and destination. So if "logic low" is 2v, you're not being at a logic low at all, hence the whole clock issue epic. In fact the logic low only happens because of undershoot. So when its crowbarred with 47R it's literally forcing the DC offset down to more like 1V and "mostly" the voltage swing is high enough to still push a logic high over 2.5v. Only on my 2 Falcons it clamps the clock down to more like 0.5v and that's not enough by far. Hence then my falcon won't boot as its clock is basically low all the time.

I solve this differently. I come from an audio background so know all about DC offsets and logic levels with MOSFET digital amps. Anyway, I don't crowbar the voltage to get it lower, I just remove the DC offset instead. I then have something like 33R to help stop ringing. But as the clock is going right across the board, all the inductance and capacitance and noise pickup all adds up. It's still there at the SDMA end,BUT the ringing / under /overshoots all happen outside of TTL logic level thresholds. So it basically doesn't matter.

So for some reason the DC offset drifts on this falcon over time which it shouldn't really be doing. This voltage very slowly increases until the logic low level gets to the point it was before all this modding was done. Basically audio crackles etc. It further drifts out then causes video issues like in the image I posted. Then eventually it just crashes and half the time won't even reset again.

Now we get back to the 100K which just pulls the clock down to 0V enough to keep the proper clock biasing. Basically you end up with like 0v to 4v on the buffer board end for example, then without the buffer board to correct the voltages, you end up with more like 2-6v on the SDMA as there is bad grounding between the 2 areas of the motherboard. With my buffer board, it auto corrects to mirror the voltage on the buffer board. So you end up with a nice clean 0-4v clock on the SDMA.




Images below show the Falcon clock patch as was fitted on my machine. This is needed on some machines which suffer from weak clock signals. The IC acts as a buffer for the clock signals. The IC used is generally a 74F04.

According to Atari documents, SCSI can suffer and can also cause DSP sound related issues such as crackling. The original Atari mod can be found HERE Though it seems steinberg revised the mod somewhat since then which is basically listed below.

Since writing these instructions I have since found a 3rd method which uses buffer resistors. My tests as to why this mod is better is listed below HERE.

I would also recommend a 100nF ceramic capacitor across the power rails of the F04 (not shown in images).




I started investigating this again because of talks with Steve about his Falcon having some minor FPU problems despite having a clock patch installed. Also the Falcon clock issues has never been properly documented anywhere to my knowledge. So I thought I would do a quick overview of all these issues.

It is actually interesting because the FPU and SDMA share the same physical clock trace on the Falcon motherboard. Generally when you mess with the SDMA clock end, you inherently change the FPU clock behaviour as well. Though I think the FPU clock end never gets the attention like the SDMA end of the signal does. Unfortunately when you terminate the SDMA clock, you also effect the clock signal on the FPU which can be suffering in logic high voltage switch can lead to FPU issues.

First let's take a look at what the actual problem is to start with.

The problems start because of a weak clock drive from the combel and how the clocks are distributed across the board.

The left side (CPUCLK) comes from the output of the Combel (normally via a resistor as well) which drives the 3 main clocks via 3x 33R resistors. It is basically standard practice to have the series resistance to help stop oscillations / ringing etc. Generally this is a good thing. Problem is, when you drive clocks from the same source they actually interfere with each other because of varying reflections from each other's traces. If one track has a lot of noise, it will backfeed the other clock lines as they are all wired together via the 33R resistors. It can even generate harmonics which further compound the issue. The problem is also compounded by Atari's very bad routing of the entire motherboard which has many "no no unnecessary right angle tracks", which increase the impedances of the tracks and make ringing even worse.

The analogy is, if you poured a bucket of water into a long guttering channel which is closed at the both ends for example. The flow of water will travel from the source (bucket) to the opposite end. When it does , the water will bounce back (reflect) from the opposite end and cause a ripple to flow back towards the source.

As I do not have a stock Falcon anymore without the clock patch. I had to do a simulation of the 3 clock signals and what one would basically look like under such a condition.

The waveform should ideally look like a square wave and not the disaster as illustrated above. If the Falcon were a real bird, we would probably just shoot it and put it out of its misery :lol:

Now enters the "classic" clock patch which the majority of clock patches are based upon. The original clock patch was to just simply fit a 74F04 inverter which can provide a good output to drive the clocks Individually. Aside from the combined clock of the FPU & SDMA that is.

It's worth noting that the Phantom clock patch uses a separate wire for the SDMA clock and is driven via slow gates on a separate IC. The SDMA should get a better clock being on its own separate wire. It is still a long distance away which is still going to cause some with ringing, though maybe not as much as with the original track. The FPU clock will still suffer from the long traces, but again, likely not as much, as the SDMA clock is decoupled from the track.

This separates the clocks and buffers them individually with a higher current driving signal. It does, however, have the side effect of increasing the ringing problems on the clock lines due to higher output current.

Take the analysis of such a clock patch on the FPU clock.

What we see here is a overshoot of over 8 volts (should be 5volts) and a undershoot of almost 3Volts. This can indeed be extremely damaging to connected chips.

Similarly on the SDMA end of the trace we have a even bigger problem.

Generally this ringing & over/undershoot, which I'll just call "noise" from here on out, is clamped by adding a small value capacitor around 100pF value or clamping it with a low value resistor. But it generally does not fully solve the problems and can result in a lower voltage clock signal. This can indeed greatly help the the SDMA clock end of the trace, but the FPU end will likely end up at a much lower voltage and can even cause FPU malfunctions.

Another problem which I have witnessed on some Falcons is that the logic low level on the SDMA clock is basically dependent on the undershoot of the signal rather than the signal's actual logic low level. The undershoot is generally on the order of 5-10ns and does not stay low long enough for the SDMA to register correctly a logic low level. The later revisions of the exxos V2 clock patch solve this problem by re-biasing the voltage levels so that the undershoot is actually undershoot from 0 volts, as it is supposed to be. The logic low level is thus corrected.

You can actually end up with something like 2v DC offset between the clock source and destination. So if the "logic low" is 2v, you're not at a logic low at all. So when it's crowbarred with a very low resistors such as 47R, it's literally forcing the DC offset down to more like 1V and "mostly" the voltage swing is high enough to still push a logic high over 2v. Basically it's sacrificing logic high voltage for more logic low voltage, while limiting the clock's peak to peak voltage. Not good basically!

However, on my two Falcons, 47R clamps the clock down to more like 0.5v (logic high!) and that's not enough by far, hence then my Falcon won't boot as its SDMA clock is basically low all the time.

So while low values such as 47R are classified as a termination resistor, which is true, it is actually crowbarring the DC offset of the clock line back down towards "normal" logic levels. It also concerns me that 47R by itself could draw up to 100mA! I seriously doubt the Combel could push that current by itself or various buffer/inverter ICs. Hence why I have been recommending for years that such a low value is simply not used.

So the natural progression of the clock patch is to add a small series resistance of generally around 33R, to the clock lines to eliminate the noise and basically cleanup the clock signals.

For example a value of 22R limits the noise as illustrated below.

FPU clock via 22R.

SDMA clock via 22R.
The exxos V2 patch has suitable resistors so the noise is reduced to levels as illustrated below on the SDMA clock.
Enter the exxos Falcon clock patch version 4.

NOTE - Information here-on-in is currently based upon version 4 prototype. Any modifications done to the Falcon are only relevant to the exxos clock patch V4 series.

V4 clock patch is a redesign and comprises two parts. While the exxos clock patch V2 series had an option for a SDMA delay to match the Phantom bus accelerator delay, it was still driving the FPU from the same SDMA clock which is not ideal but generally works for 99% of people. So I wanted to add more variation of delays to improve the signals of the SDMA and FPU clocks Individually.

Part 1: - For stock machines.

Looks generally familiar as most classic clock patches do. It fits the same way as the V2 but now the board includes separate noise immune buffers which have a higher output voltage drive than the original clock patches do with the 74F04 inverter. A side effect of this is that there are no longer any "free" inverters to mimic the Phantom delay to the SDMA. This is where Part 2 of the V4 clock patch comes into play which is explained later.

At this point you do not necessarily need the part 2 board If you are just running a stock Falcon. You can cut the "bootleg trace" near the SDMA and insert a 68R resistor across the now cut track. Then to the right-hand side closest to the SDMA, connect a 100pF capacitor to the Ajax GND pin.

This cleans up the SDMA clock which now looks like below.

Previously it would look like this (This is including the FPU 100pF added in the steps below.)
The FPU clock needs 100pF added which has to be done on the bottom of the Falcon motherboard as illustrated below.
The FPU clock now looks like this.
Part 2: - For experimenters with bus speeders.
This part fits on top of the Ajax chip and two pins are soldered for power. This board has noise immune buffers which clean up the signal from the SDMA trace and allow the option of various delays in 10ns increments for experimentation with bus speeders.

The bootleg trace gets cut. The left-hand side of the trace goes to the input of the SDMA buffer board on the left. The right-hand side of the cut track (SDMA side) goes to one of the pads on the top of the buffer board. These are basically in 10ns steps. Technically the first step is about 5ns due to buffer delays. But on the final revision board it will be classified as 0ns.

So what the hell does all this mean?

What we have done is create a new clock buffer board with higher output capabilities and better noise immunity. This still drives the FPU clock directly, but now is terminated with a 100pF capacitor. Any "noise" reflected back from the SDMA trace is basically snubbed out by the patch board. Any noise which is heading towards the FPU clock is snubbed out by the 100pF on the FPU clock anyway.

There is no need anymore to route a separate SDMA clock wire like on the phantom clock patch. It was part of my design goal to make use of the original SDMA trace and not using a separate wire. Noise on the SDMA clock is minimised because we are no longer driving the SDMA clock directly from the clock patch board. The Falcon's clock traces and related issues become basically irrelevant. Any noise present at this point will be snubbed out by the buffer board on top of the AJAX. The SDMA will get the most noise-free and stable clock possible due to it being driven locally.

Some more investigations due to what is "seen" on the buffer end of the clock patch. Mostly just out of curiosity more than anything.

NOTE: The clock buffer output goes via a 22R resistor and all measurements are taken AFTER the resistor. Measurements were all done with a X10 probe. X1 is not used due to limited bandwidth and additional capacitance which would be tainting the results. The probe was calibrated before the tests as well. There may be some errors in measurement still, i.e. the real under/overshoot is likely a little less than is seen. But for these quick experiments I am not to fussed anyway. Dave Jones has a great video on scope probes if anyone's interested in this stuff.

OK so I did a "worst case" grounding test and a "best case" test.

The worst case grounding is this.

Best case:
In the above test the ground lead is removed from the scope probe and a short wire is used instead which goes directly to the FPU 0v pin. Only about 5% difference. Good enough margin for error for the test I wanted to do anyway.

Again if anyone's interested, Texas Instruments has a very good article on probing problems.

So let's just get on with it :)

With the 100pF on the bottom of the FPU clock, it actually gives this waveform on the actual clock patch board itself.The FPU clock is perfectly fine still.

I have seen such a "glitch" On the rise and fall before, when building digital power amplifiers, called "Miller plateau". Though in the case of transmission lines, it seems to be a side effect of the capacitor charging. When charging, its varying impedances cause a negative reflection which causes the glitches in the rise and fall part of the waveform. So I thought I would do some experiments with varying "termination" styles to see if I could improve on anything.

Series termination is already explained in the post above where simply a low value resistor of typically 22R is used in series with the track to limit the reflections.

Parallel termination is already explained above, with a capacitor "shunt". Its impedance (effective resistance) is about 100R. So in this first test I simply tried a 100R resistor on the FPU to terminate it to gnd.


Sees the return of the under & overshoot. But interestingly the overshoot isn't actually a overshoot as it doesn't get above 5v.


Has cured the "glitches" in the rise and fall but overall it is still a little bit "rough".

Lowering the resistor from 100R to 45R did not have much effect other than limiting the overall voltage.

Incidentally, adding or removing the series 22R resistor also had no effect other than limiting the overall voltage. Subsequent tests also yielded similar results.

Next up was to try "AC termination". This is with a resistor in series with the capacitor. Again this is done under the FPU.

FPU CLOCK 100R 100pF.

FPU CLOCK 45R 100pF.
So with the AC type termination it does not really change anything other than you can either have a good clock on one end or the other, but not both!

Next up is the "Thevenin Parallel" Termination Network. Basically this has a pull-up on the FPU clock to 5V and pull down to 0V. The resistors used were 100R.


So again not a ideal solution. But it's not bad either. Shorting the 22R makes the voltages higher but also introduces more under/overshoot. Using higher values than 100R may well improve the logic level, but again we would inherently be increasing the under/overshoot spikes.

There is also diode termination but I do not have suitable fast diodes to try this experiment. But if I remember rightly when I tried this years ago, the hard crowbarring of the voltage actually caused ringing to become worse. Adding a resistor across the capacitor is a parallel termination network basically ended up making things worse overall. I did not document those results.

While the 100R termination resistor does not cure the under and overshoot problem as such, it does not "glitch" on the buffer driver either. The overshoot is actually only up to 5V, so a logic one is sustained above 4V anyway. The undershoot is still rather a lot. So I don't class it as a ideal solution in terms of protecting the FPU clock.

So, while capacitors can indeed cure the over and undershoot problems on the FPU clock, it seems it just basically shifts the problem over to the opposite end of the track and dumps it onto the buffer driver instead. So adding 22R series resistance ensures the driver doesn't get such abuse like shown in the images. The only real downfall is the rise and fall times of the clock are slowed down slightly. But I doubt it would make any difference anyway. Using resistors, we can indeed remain between 0V-5V, still with ringing present, and with lowered logic one voltage to about 4V.

While we could be theoretically improve on the resistor situation, I think the problem is we are basically dealing with a three-way termination line. Resistors could possibly work well for a normal "single" line. But we are basically dealing with a 'Y-shape" track, so things are just never going to be simple.

There are more complex solutions to solve such issues, but I feel it's getting to the point of simply being over complicated. There could be many more ways to "solve" the issues and maybe even better values to what I have used. Though even if better values were found, it may not work on a different machine anyway. One could spend several months experimenting with it all. It was just my intention to do a quick experiment with various termination styles more than anything to see what the differences were basically.

The ideal solution would just to just cut the FPU clock and drive it from its own oscillator instead. Like with my FPU clock boards I designed some years ago. This way the FPU is driven locally and won't suffer the same as being driven from the clock patch board.

Overall sticking with a 100pF on the FPU clock is the best cleanup. While we get some nasty signals bouncing back to the driver board, they are basically snubbed out via the 22R anyway. So overall this just seems to be the best compromise.

I also must stress again, that the install or modifications of the V4 clock patch should not be "back ported" to older clock patch designs. The V4 series solves more problems than the original designs and you cannot "mix and match" parts of the V4 design to any other older clock patches.


"Part 2" of the V4 patch has been abandoned. It was mostly a experiment for accelerators which was to allow people experimentation with various delays. However, I later read that during the Phantom clock patch investigation by presumably its original author, he documented that even changing the brand of the second buffer chip driving the SDMA clock was enough to cause problems. So it seems to me that the delay has to be literally nanoseconds perfect in order to function at the speed it does. I'm not a fan of such tight tolerances because you can easily get a couple of nanoseconds delays depending on temperature and tolerances on chips. However as part of my investigation that is simply not worth spending any more time on it. Regrettably at the time of typing I cannot remember where I read that information.

The V4 Falcon clock patch went into a small production run as version 4.2A. At the time of typing it is classed as a Alpha version. As described investigation above, it is designed to solve more clock driving problems on the Falcon motherboard which the original designs do not address. This kit should not be attempted unless you have good soldering skills.